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High Accuracy, Ultralow IQ, 500 mA, anyCAP(R) Low Dropout Regulator ADP3335
FEATURES
High accuracy over line and load: 0.9% @ 25C, 1.8% over temperature Ultralow dropout voltage: 200 mV (typ) @ 500 mA Requires only CO = 1.0 F for stability anyCAP = stable with any type of capacitor (Including MLCC) Current and thermal limiting Low noise Low shutdown current: < 10 nA (typ) 2.6 V to 12 V supply range -40C to +85C ambient temperature range
IN THERMAL PROTECTION
FUNCTIONAL BLOCK DIAGRAM
Q1 OUT
ADP3335
CC DRIVER
R1 NR
gm R2 BANDGAP + REF -
00147-0-001
SD
GND
Figure 1.
5
APPLICATIONS
PCMCIA cards Cellular phones Camcorders, cameras Networking systems, DSL/cable modems Cable set-top box MP3/CD players DSP supplies
NR
ADP3335
OUT 3
7 IN
OUT 2 OUT 1 GND
4
VIN
CIN 1F
+
8 IN
SD
6
+
COUT 1F
VOUT
ON OFF
Figure 2. Typical Application Circuit
GENERAL DESCRIPTION
The ADP3335 is a member of the ADP333x family of precision, low dropout, anyCAP voltage regulators. It operates with an input voltage range of 2.6 V to 12 V, and delivers a continuous load current up to 500 mA. The ADP3335 stands out from conventional low dropout regulators (LDOs) by using an enhanced process enabling it to offer performance advantages beyond its competition. Its patented design requires only a 1.0 F output capacitor for stability. This device is insensitive to output capacitor equivalent series resistance (ESR), and is stable with any good quality capacitor--including ceramic (MLCC) types for space-restricted applications. The ADP3335 achieves exceptional accuracy of 0.9% at room temperature and 1.8% over temperature, line, and load. The dropout voltage of the ADP3335 is only 200 mV (typical) at 500 mA. This device also includes a safety current limit, thermal overload protection, and a shutdown feature. In shutdown mode, the ground current is reduced to less than 1 A. The ADP3335 has a low quiescent current of 80 A (typical) in light load situations.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
00147-0-002
ADP3335 TABLE OF CONTENTS
Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Pin Configuration and Function Descriptions............................. 5 Typical Performance Characteristics ............................................. 6 Theory of Operation ........................................................................ 9 Application Information................................................................ 10 Output Capacitor Selection....................................................... 10 Input Bypass Capacitor.............................................................. 10 Noise Reduction ......................................................................... 10 Thermal Overload Protection .................................................. 10 Calculating Junction Temperature........................................... 10 Printed Circuit Board Layout Considerations........................ 11 LFCSP Layout Considerations.................................................. 11 Shutdown Mode ......................................................................... 11 Outline Dimensions ....................................................................... 12 Ordering Guide .......................................................................... 13
REVISION HISTORY
1/04 changed from Rev. 0 to Rev. A Format updated...............................................................Universal Renumbered figures .......................................................Universal Removed Figure 22....................................................................... 6 Change to Printed Circuit Board Layout Considerations section.................................................. 11 Added LFCSP Layout Considerations section........................ 11 Added Package Drawing................................................Universal Changes to Ordering Guide ...................................................... 16
Rev. A | Page 2 of 16
ADP3335 SPECIFICATIONS
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods. Ambient temperature of 85C corresponds to a junction temperature of 125C under pulsed full-load test conditions. Application stable with no load. VIN = 6.0 V, CIN = COUT = 1.0 F, TA = -40C to +85C, unless otherwise noted. Table 1.
Parameter OUTPUT Voltage Accuracy1 Symbol VOUT Conditions VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TA = 25C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TA = 85C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA to 500 mA TJ = 150C VIN = VOUT(NOM) + 0.4 V to 12 V IL = 0.1 mA TA = 25C IL = 0.1 mA to 500 mA TA = 25C VOUT = 98% of VOUT(NOM) IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) + 1 V f = 10 Hz to 100 kHz, CL = 10 F IL = 500 mA, CNR = 10 nF f = 10 Hz to 100 kHz, CL = 10 F IL = 500 mA, CNR = 0 nF IL = 500 mA IL = 300 mA IL = 50 mA IL = 0.1 mA VIN = VOUT(NOM) - 100 mV IL = 0.1 mA SD = 0 V, VIN = 12 V ON OFF 0 SD 5 V VIN = 12 V, VOUT = 0 V 2.0 1.2 0.01 0.4 3 5 Min -0.9 Typ Max +0.9 Unit %
-1.8
+1.8
%
-2.3
+2.3
%
Line Regulation1
0.04
mV/V
Load Regulation Dropout Voltage VDROP
0.04
mV/mA
Peak Load Current Output Noise
ILDPK VNOISE
200 140 30 10 800 47 95
370 230 110 40
mV mV mV mV mA V rms V rms
GROUND CURRENT In Regulation
IGND
In Dropout In Shutdown SHUTDOWN Threshold Voltage SD Input Current Output Current in Shutdown
IGND IGNDSD VTHSD ISD IOSD
4.5 2.6 0.5 80 120 0.01
10 6 2.5 110 400 1
mA mA mA A A A V V A A
1
VIN = 2.6 V to 12 V for models with VOUT(NOM) 2.2 V.
Rev. A | Page 3 of 16
ADP3335 ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Input Supply Voltage Shutdown Input Voltage Power Dissipation Operating Ambient Temperature Range Operating Junction Temperature Range JA, 2-layer MSOP-8 JA, 4-layer MSOP-8 JA, 2-layer LFCSP-8 JA, 4-layer LFCSP-8 Storage Temperature Range Lead Temperature Range (Soldering 10 sec) Vapor Phase (60 sec) Infrared (15 sec) Rating -0.3 V to +16 V -0.3 V to +16 V Internally Limited -40C to +85C -40C to +150C 220C/W 158C/W 62C/W 48C/W -65C to +150C 300C 215C 220C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. A | Page 4 of 16
ADP3335 PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
OUT 1 OUT 2 OUT 3 GND 4
8
IN IN
00147-0-022 00147-0-025
ADP3335
TOP VIEW (Not to Scale)
7 6 5
SD NR
Figure 3. 8-Lead MSOP
OUT 1 OUT 2 OUT 3
8
IN
IN TOP VIEW 6 SD (Not to Scale) GND 4 5 NR
7
ADP3335
Figure 4. 8-Lead LFCSP
Table 3. Pin Function Descriptions
Pin No. 1, 2, 3 4 5 6 7, 8 Mnemonic OUT GND NR SD IN Function Output of the Regulator. Bypass to ground with a 1.0 F or larger capacitor. All pins must be connected together for proper operation. Ground Pin. Noise Reduction Pin. Used for further reduction of output noise (see the Noise Reduction section for further details). Active Low Shutdown Pin. Connect to ground to disable the regulator output. When shutdown is not used, this pin should be connected to the input pin. Regulator Input. All pins must be connected together for proper operation.
Rev. A | Page 5 of 16
ADP3335 TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25C, unless otherwise noted
2.202 VOUT = 2.2V 2.201 2.200
OUTPUT VOLTAGE (V)
5.0
IL = 0
GROUND CURRENT (A)
4.0
2.199 150mA 2.198 2.197 2.196 300mA 2.195 500mA 2.194 2 4 6 8 INPUT VOLTAGE (V) 10
00147-0-003
3.0
2.0
1.0
00147-0-006
12
0
0
100
200 300 LOAD CURRENT (mA)
400
500
Figure 5. Line Regulation Output Voltage vs. Supply Voltage
2.201 2.200 2.199
OUTPUT VOLTAGE (V)
Figure 8. Ground Current vs. Load Current
1.0 0.9 0.8 0.7 300mA 0.6 0.5 0.4 0.3 0.2 0.1 0 -0.1
00147-0-004
VOUT = 2.2V VIN = 6V
0
2.198 2.197 2.196 2.195 2.194 2.193 0 100 200 300 LOAD CURRENT (mA) 400
OUTPUT CHANGE (%)
500mA
-0.3
500
-0.4 -40
-15
5 25 45 65 85 JUNCTION TEMPERATURE (C)
105
125
Figure 6. Output Voltage vs. Load Current
140 IL = 100A 120 VOUT = 2.2V
Figure 9. Output Voltage Variation vs. Junction Temperature
8 IL = 500mA 7
GROUND CURRENT (mA)
GROUND CURRENT (A)
100 80 60 40 IL = 0
6 5 300mA 4 3 2 100mA 50mA 0 -15 45 65 85 5 25 JUNCTION TEMPERATURE (C) 105
00147-0-008
00147-0-005
20 0
1 0 -40
0
2
4 6 8 INPUT VOLTAGE (V)
10
12
125
Figure 7. Ground Current vs. Supply Voltage
Figure 10. Ground Current vs. Junction Temperature
Rev. A | Page 6 of 16
00147-0-007
-0.2
500mA
ADP3335
250
2.210
200
DROPOUT VOLTAGE (mV)
VOUT (V)
2.200 2.190
150
VOUT = 2.2V
2.189
RL = 4.4 CL = 1F
100
2.179
50
00147-0-009
VIN (V)
3.500 3.000
00147-0-012
0
0
100
200 300 OUTPUT (mA)
400
500
40
80
140 TIME (s)
180
Figure 11. Dropout Voltage vs. Output Current
Figure 14. Line Transient Response
3.0
INPUT/OUTPUT VOLTAGE (V)
VOUT = 2.2V SD = VIN RL = 4.4
2.210 2.200 2.190
2.0 1.5 1.0 0.5
00147-0-010
VOUT (V)
2.5
VOUT = 2.2V
2.189 2.179
RL = 4.4 CL = 10F
3.000
1
2
3
4
40
80
TIME (sec)
140 TIME (s)
180
Figure 12. Power-Up/Power-Down
Figure 15. Line Transient Response
3 COUT = 1F
2.3
VOUT (V)
VOUT (V)
2 1 0 4 COUT = 10F
2.2 2.1 VIN = 4V VOUT = 2.2 CL = 1F
400
ILOAD (mA)
VIN (V)
2
00147-0-011
200 0
00147-0-014
0
VOUT = 2.2V SD = VIN RL = 4.4 200 600 400 TIME (s) 800
200
400 600 TIME (s)
800
Figure 13. Power-Up Response
Figure 16. Load Transient Response
Rev. A | Page 7 of 16
00147-0-013
0
VIN (V)
3.500
ADP3335
-20 VOUT = 2.2V
2.3
VOUT (V)
-30
RIPPLE REJECTION (dB)
2.2 2.1 VIN = 4V RL = 4.4 CL = 10F
-40 -50 -60 -70 -80 -90 CL = 1F IL = 50A
CL = 1F IL = 500mA
CL = 10F IL = 500mA
ILOAD (mA)
400 200
00147-0-015
200
400
600 TIME (s)
800
10
100
1k
10k 100k FREQUENCY (Hz)
1M
10M
Figure 17. Load Transient Response
160
Figure 20. Power Supply Ripple Rejection
CNR = 10nF
VOUT (V)
2.2 0
RMS NOISE (V)
140 120 100 80 60 40
00147-0-016
IL = 500mA WITHOUT NOISE REDUCTION
3
ILOAD (A)
800m SHORT
FULL SHORT
IL = 500mA WITH NOISE REDUCTION IL = 0mA WITHOUT NOISE REDUCTION
2 1 0 VIN = 4V
20 IL = 0mA WITH NOISE REDUCTION 0 0 10 20 CL (F) 30 40 50
200
400 600 TIME (s)
800
Figure 18. Short-Circuit Current
Figure 21. RMS Noise versus CL (10 Hz to 100 kHz)
3 1F
VIN = 4V VOUT = 2.2V RL = 4.4
100 VOUT = 2.2V IL = 1mA
VOLTAGE NOISE SPECTRAL DENSITY (V/ Hz)
VOUT (V)
2 10F 1 0 1F 10F
10
CL = 10F CNR = 10nF
CL = 10F CNR = 0nF
CL = 1F CNR = 0nF
1
0.1 CL = 1F CNR = 10nF 0.01
00147-0-020
VSD (V)
2 1
00147-0-017
200
600 400 TIME (s)
800
0.001
10
100
1k 10k FREQUENCY (Hz)
100k
1M
Figure 19. Turn On/Turn Off Response
Figure 22. Output Noise Density
Rev. A | Page 8 of 16
00147-0-019
00147-0-018
0
CL = 10F IL = 50A
ADP3335 THEORY OF OPERATION
The ADP3335 uses a single control loop for regulation and reference functions. The output voltage is sensed by a resistive voltage divider, R1 and R2, which is varied to provide the available output voltage option. Feedback is taken from this network by way of a series diode, D1, and a second resistor divider, R3 and R4, to the input of an amplifier.
INPUT Q1 NONINVERTING WIDEBAND DRIVER OUTPUT COMPENSATION ATTENUATION R1 CAPACITOR (VBANDGAP/VOUT) D1 R3 PTAT (a) gm VOS PTAT R4 CURRENT R2
divider--R3 and R4, the values can be chosen to produce a temperature stable output. This unique arrangement specifically corrects for the loading of the divider, thus avoiding the error resulting from base current loading in conventional circuits. The patented amplifier controls a new and unique noninverting driver that drives the pass transistor, Q1. This special noninverting driver enables the frequency compensation to include the load capacitor in a pole-splitting arrangement to achieve reduced sensitivity to the value, type, and ESR of the load capacitance. Most LDOs place very strict requirements on the range of ESR values for the output capacitor, because they are difficult to stabilize due to the uncertainty of load capacitance and resistance. The ESR value required to keep conventional LDOs stable, moreover, changes depending on load and temperature. These ESR limitations make designing with LDOs more difficult because of their unclear specifications and extreme variations over temperature. With the ADP3335, ESR limitations are no longer a source of design constraints. The ADP3335 can be used with virtually any good quality capacitor and with no constraint on the minimum ESR. This innovative design allows the circuit to be stable with just a small 1 F capacitor on the output. Additional advantages of the pole-splitting scheme include superior line noise rejecttion and very high regulator gain, which lead to excellent line and load regulation. Impressive 1.8% accuracy is guaranteed over line, load, and temperature. Additional features of the circuit include current limit, thermal shutdown, and noise reduction.
CLOAD RLOAD
00147-0-023
ADP3335
GND
Figure 23. Functional Block Diagram
A very high gain error amplifier is used to control this loop. The amplifier is constructed in such a way that equilibrium produces a large, temperature proportional input offset voltage that is repeatable and very well controlled. The temperature proportional offset voltage combines with the complementary diode voltage to form a virtual band gap voltage implicit in the network, although it never appears explicitly in the circuit. This patented design makes it possible to control the loop with only one amplifier. This technique also improves the noise characteristics of the amplifier by providing more flexibility in the trade-off of noise sources that leads to a low noise design. The R1 and R2 divider is chosen in the same ratio as the band gap voltage to the output voltage. Although the R1 and R2 resistor divider is loaded by the D1 diode and a second
Rev. A | Page 9 of 16
ADP3335 APPLICATION INFORMATION
OUTPUT CAPACITOR SELECTION
As with any micropower device, output transient response is a function of the output capacitance. The ADP3335 is stable over a wide range of capacitor values, types, and ESR (anyCAP). A capacitor as low as 1 F is all that is needed for stability; larger capacitors can be used if high output current surges are anticipated. The ADP3335 is stable with extremely low ESR capacitors (ESR 0), such as multilayer ceramic capacitors (MLCC) or organic semiconductor electrolytic capacitors (OSCON). Note that the effective capacitance of some capacitor types may fall below the minimum at extreme temperatures. Ensure that the capacitor provides more than 1 F over the entire temperature range.
THERMAL OVERLOAD PROTECTION
The ADP3335 is protected against damage from excessive power dissipation by its thermal overload protection circuit, which limits the die temperature to a maximum of 165C. Under extreme conditions (i.e., high ambient temperature and power dissipation) where die temperature starts to rise above 165C, the output current is reduced until the die temperature has dropped to a safe level. The output current is restored when the die temperature is reduced. Current and thermal limit protections are intended to protect the device against accidental overload conditions. For normal operation, device power dissipation should be externally limited so that junction temperatures will not exceed 150C.
INPUT BYPASS CAPACITOR
An input bypass capacitor is not strictly required, but is advisable in any application involving long input wires or high source impedance. Connecting a 1 F capacitor from IN to ground reduces the circuit's sensitivity to PC board layout. If a larger value output capacitor is used, then a larger value input capacitor is also recommended.
CALCULATING JUNCTION TEMPERATURE
Device power dissipation is calculated as follows:
PD = (VIN - VOUT )I LOAD + (VIN )IGND
NOISE REDUCTION
A noise reduction capacitor (CNR) can be used, as shown in Figure 24, to further reduce the noise by 6 dB to 10 dB (Figure 22). Low leakage capacitors in the 100 pF to 1 nF range provide the best performance. Since the noise reduction pin, NR, is internally connected to a high impedance node, any connection to this node should be made carefully to avoid noise pickup from external sources. The pad connected to this pin should be as small as possible, and long PC board traces are not recommended. When adding a noise reduction capacitor, maintain a minimum load current of 1 mA when not in shutdown. It is important to note that as CNR increases, the turn-on time will be delayed. With NR values greater than 1 nF, this delay may be on the order of several milliseconds.
CNR
Where ILOAD and IGND are load current and ground current, and VIN and VOUT are input and output voltages, respectively. Assuming ILOAD = 400 mA, IGND = 4 mA, VIN = 5.0 V, and VOUT = 3.3 V, device power dissipation is PD = (5 V - 3.3 V)400 mA + 5.0 V(4 mA) = 700 mW The junction temperature can be calculated from the power dissipation, ambient temperature, and package thermal resistance. The thermal resistance is a function not only of the package, but also of the circuit board layout. Standard test conditions are used to determine the values published in this data sheet, but actual performance will vary. For an LFCSP-8 package mounted on a standard 4-layer board, JA is 48C/W. In the above example, where the power dissipation is 700 mW, the temperature rise above ambient will be approximately equal to TJA = 0.700 W x 48C/W = 33.6C To limit the maximum junction temperature to 150C, the maximum allowable ambient temperature will be TAMAX = 150C - 33.6C = 116.4C
5
NR OUT 3
ADP3335
7 IN
OUT 2 OUT 1 GND
4
In this case, the resulting ambient temperature limitation is above the maximum allowable ambient temperature of 85C.
+ VOUT COUT 1F
00147-0-021
VIN
CIN 1F
+
8 IN
SD
6
ON OFF
Figure 24. Typical Application Circuit
Rev. A | Page 10 of 16
ADP3335
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
All surface-mount packages rely on the traces of the PC board to conduct heat away from the package. Use the following general guidelines when designing printed circuit boards to improve both electrical and thermal performance. 1. 2. 3. Keep the output capacitor as close as possible to the output and ground pins. Keep the input capacitor as close as possible to the input and ground pins. PC board traces with larger cross sectional areas will remove more heat from the ADP3335. For optimum heat transfer, specify thick copper and use wide traces. It is not recommended to use solder mask or silkscreen on the PCB traces adjacent to the ADP3335's pins, since doing so will increase the junction-to-ambient thermal resistance of the package. Use additional copper layers or planes to reduce the thermal resistance. When connecting to other layers, use multiple vias, if possible. 3. 2. The thermal pad of the LFCSP package provides a low thermal impedance path (approximately 20C/W) to the PCB. Therefore, the PCB must be properly designed to effectively conduct heat away from the package. This is achieved by adding thermal vias to the PCB, which provide a thermal path to the inner or bottom layers. See Figure 25 for the recommended via pattern. Note that the via diameter is small to prevent the solder from flowing through the via and leaving voids in the thermal pad solder joint. Also, note that the thermal pad is attached to the die substrate, so the thermal planes to which the thermal vias connect must be electrically isolated or tied to VIN. Do NOT connect the thermal pad to ground. The solder mask opening should be about 120 (4.7 mils) larger than the pad size, resulting in a minimum 60 m (2.4 mils) clearance between the pad and the solder mask. The paste mask opening is typically designed to match the pad size used on the peripheral pads of the LFCSP package. This should provide a reliable solder joint as long as the stencil thickness is about 0.125 mm. The paste mask for the thermal pad needs to be designed for the maximum coverage to effectively remove the heat from the package. However, due to the presence of thermal vias and the size of the thermal pad, eliminating voids may not be possible. The recommended paste mask stencil thickness is 0.125 mm. A laser cut stainless steel stencil with trapezoidal walls should be used. A "No Clean" Type 3 solder paste should be used for mounting the LFCSP package. Also, a nitrogen purge during the reflow process is recommended. The package manufacturer recommends that the reflow temperature should not exceed 220C and the time above liquidus is less than 75 seconds. The preheat ramp should be 3C/second or lower. The actual temperature profile depends on the board density and must be determined by the assembly house as to what works best.
4.
4.
5.
LFCSP LAYOUT CONSIDERATIONS
The LFCSP package has an exposed die paddle on the bottom, which efficiently conducts heat to the PCB. In order to achieve the optimum performance from the LFCSP package, special consideration must be given to the layout of the PCB. Use the following layout guidelines for the LFCSP package.
2x VIAS, 0.250 35m PLATING 0.73 0.30 1.80 0.90 0.50 2.36
5.
6.
1.40 1.90 3.36
00147-0-024
SHUTDOWN MODE
Applying a TTL high signal to the shutdown (SD) pin or tying it to the input pin, turns the output ON. Pulling SD down to 0.4 V or below, or tying it to ground, turns the output OFF. In shutdown mode, quiescent current is reduced to a typical value of 10 nA.
Figure 25. 3 mm x 3 mm LFCSP Pad Pattern (Dimensions shown in millimeters)
1.
The pad pattern is given in Figure 25. The pad dimension should be followed closely for reliable solder joints, while maintaining reasonable clearances to prevent solder bridging.
Rev. A | Page 11 of 16
ADP3335 OUTLINE DIMENSIONS
3.00 BSC SQ 0.45
8
0.60 MAX
0.50 0.40 0.30
PIN 1 INDICATOR
1
PIN 1 INDICATOR
TOP VIEW
2.75 BSC SQ
0.50 BSC 0.25 MIN
BO TTOM VIEW
5 4
1.50 REF
1.90 1.75 1.60
0.90 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.30 0.23 0.18 0.20 REF
1.60 1.45 1.30
SEATING PLANE
Figure 26. 8-Lead Frame Chip Scale Package [LFCSP] (CP-8) Dimensions shown in millimeters
3.00 BSC
8
5
3.00 BSC
4
4.90 BSC
PIN 1 0.65 BSC 1.10 MAX 8 0 0.80 0.60 0.40
0.15 0.00 0.38 0.22 COPLANARITY 0.10
0.23 0.08 SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MO-187AA
Figure 27. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters
Rev. A | Page 12 of 16
ADP3335
ORDERING GUIDE
Model ADP3335ARM-1.8-RL ADP3335ARM-1.8-RL7 ADP3335ARM-2.5-RL ADP3335ARM-2.5-RL7 ADP3335ARMZ-2.5-RL72 ADP3335ARM-2.85-RL ADP3335ARM-2.85-R7 ADP3335ARMZ-2.85-R72 ADP3335ARM-3.3-RL ADP3335ARMZ-3.3-RL2 ADP3335ARM-3.3-RL7 ADP3335ARM-5-REEL ADP3335ARM-5-REEL7 ADP3335ACP-1.8-RL ADP3335ACP-1.8-RL7 ADP3335ACP-2.5-RL ADP3335ACP-2.5-RL7 ADP3335ACP-2.85-R7 ADP3335ACP-3.3-RL ADP3335ACP-3.3-RL7 ADP3335ACP-5-REEL ADP3335ACP-5-REEL7 Output Voltage1 1.8 V 1.8 V 2.5 V 2.5 V 2.5 V 2.85 V 2.85 V 2.85 V 3.3 V 3.3 V 3.3 V 5V 5V 1.8 V 1.8 V 2.5 V 2.5 V 2.85 V 3.3 V 3.3 V 5V 5V Package Option RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) RM-8 (MSOP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) CP-8 (LFCSP-8) Branding Information LFA LFA LFC LFC LFC3 LFD LFD LFD3 LFE LFE3 LFE LFF LFF LFA LFA LFC LFC LFD LFE LFE LFF LFF
1 2
Contact the factory for other output voltage options. Z = Pb-free part. 3 Pb-free devices have a "#" marked on the device.
Rev. A | Page 13 of 16
ADP3335 NOTES
Rev. A | Page 14 of 16
ADP3335 NOTES
Rev. A | Page 15 of 16
ADP3335 NOTES
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners C00147-0-1/04(A)
Rev. A | Page 16 of 16

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